SiDB Lattice Layout
The SiDB lattice layout can be layered on top of an SiDB cell-level layout. It is used to store and access the H-Si lattice orientation (H-Si(100)-2x1 surface or H-Si(111)-1x1 surface).
Header: fiction/technology/sidb_lattice.hpp
-
template<typename LatticeOrientation, typename Lyt, bool has_sidb_lattice_interface = is_sidb_lattice_v<Lyt>>
class sidb_lattice : public Lyt A layout type to layer on top of an SiDB cell-level layout. It implements an interface for different lattice orientations of the H-Si crystal.
- Template Parameters:
LatticeOrientation – Type of the lattice orientation.
Lyt – SiDB cell-level layout type.
has_sidb_lattice_interface – Automatically determines whether an SiDB lattice interface is already present.
- class mnt.pyfiction.sidb_lattice_100
A layout type to layer on top of a clocked layout that allows the assignment of individual cells to clock zones in accordance with an FCN technology, e.g., QCA, iNML, or SiDB. This type, thereby, represents layouts on a cell-accurate abstraction without a notion of logic functions. Gate libraries can be used to transform gate-level layouts into cell-level ones. Furthermore, cell-level layouts can be written to files for various physical simulators like QCADesigner, ToPoliNano & MagCAD, SiQAD, etc.
In this layout, each coordinate, i.e., clock zone has the dimensions of a single cell. Clock numbers can, however, be assigned in a way, that they form larger zones, e.g., of \(5 \times 5\) cells. These dimensions can be specified in the constructor. They affect the way, clock numbers are fetched from the underlying clocked layout.
The de-facto standard of cell-level FCN design is to group multiple cells into tiles large enough to be addressable by individual clocking electrodes buried in the layout substrate. Cell-based clocking, i.e., clock zones of size \(1 \times 1\) cells are not recommended as they are most likely not fabricable in reality.
On the implementation side, this layout distinguishes between cell, cell_type, and cell_mode. A cell is a coordinate, i.e., a position on the layout where a cell_type can be assigned. A cell_type is a concrete variation of a fabricated cell and depends on the given technology. QCA offers regular and constant cell types while SiDB only provides regular ones. Cell types can also include primary input and output cells if they are being treated differently in a simulator for instance. A cell_mode, on the other hand, is a variation of a cell (thus far only known from QCADesigner) that provides further attributes like its functionality as a crossing or via cell.
- Template parameter
Technology: An FCN technology that provides notions of cell types.
- Template parameter
ClockedLayout: The clocked layout that is to be extended by cell positions.
- Template parameter
- class mnt.pyfiction.sidb_lattice_111
A layout type to layer on top of a clocked layout that allows the assignment of individual cells to clock zones in accordance with an FCN technology, e.g., QCA, iNML, or SiDB. This type, thereby, represents layouts on a cell-accurate abstraction without a notion of logic functions. Gate libraries can be used to transform gate-level layouts into cell-level ones. Furthermore, cell-level layouts can be written to files for various physical simulators like QCADesigner, ToPoliNano & MagCAD, SiQAD, etc.
In this layout, each coordinate, i.e., clock zone has the dimensions of a single cell. Clock numbers can, however, be assigned in a way, that they form larger zones, e.g., of \(5 \times 5\) cells. These dimensions can be specified in the constructor. They affect the way, clock numbers are fetched from the underlying clocked layout.
The de-facto standard of cell-level FCN design is to group multiple cells into tiles large enough to be addressable by individual clocking electrodes buried in the layout substrate. Cell-based clocking, i.e., clock zones of size \(1 \times 1\) cells are not recommended as they are most likely not fabricable in reality.
On the implementation side, this layout distinguishes between cell, cell_type, and cell_mode. A cell is a coordinate, i.e., a position on the layout where a cell_type can be assigned. A cell_type is a concrete variation of a fabricated cell and depends on the given technology. QCA offers regular and constant cell types while SiDB only provides regular ones. Cell types can also include primary input and output cells if they are being treated differently in a simulator for instance. A cell_mode, on the other hand, is a variation of a cell (thus far only known from QCADesigner) that provides further attributes like its functionality as a crossing or via cell.
- Template parameter
Technology: An FCN technology that provides notions of cell types.
- Template parameter
ClockedLayout: The clocked layout that is to be extended by cell positions.
- Template parameter