SiDB Gate Designer

C++Python

Header: fiction/algorithms/physical_design/design_sidb_gates.hpp

struct design_sidb_gates_stats

Statistics for the design of SiDB gates.

Public Functions

inline void report(std::ostream &out = std::cout) const

This function outputs the total time taken for the SiDB gate design process to the provided output stream. If no output stream is provided, it defaults to standard output (std::cout).

Parameters:

out – The output stream to which the report will be written.

Public Members

mockturtle::stopwatch::duration time_total = {0}

The total runtime of SiDB gate design process.

mockturtle::stopwatch::duration pruning_total = {0}

The runtime of the pruning process.

sidb_simulation_engine sim_engine = {sidb_simulation_engine::QUICKEXACT}

The simulation engine to be used for the operational domain computation.

std::size_t number_of_layouts = {0}

The number of all possible layouts.

std::size_t number_of_layouts_after_first_pruning = {0}

The number of layouts that remain after first pruning (discarding layouts with potential positive SiDBs).

std::size_t number_of_layouts_after_second_pruning = {0}

The number of layouts that remain after second pruning (discarding layouts that fail to satisfy the physical model).

std::size_t number_of_layouts_after_third_pruning = {0}

The number of layouts that remain after third pruning (discarding layouts with unstable I/O signals).

template<typename CellType>
struct design_sidb_gates_params

This struct contains parameters and settings to design SiDB gates.

Template Parameters:

CellType – Cell type.

Public Types

enum class termination_condition : uint8_t

Selector for the different termination conditions for the SiDB gate design process.

Values:

enumerator AFTER_FIRST_SOLUTION

The design process is terminated as soon as the first valid SiDB gate design is found.

enumerator ALL_COMBINATIONS_ENUMERATED

The design process ends after all possible combinations of SiDBs within the canvas are enumerated.

enum class design_sidb_gates_mode : uint8_t

Selector for the available design approaches.

Values:

enumerator QUICKCELL

Gates are designed by using QuickCell.

enumerator AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER

Gates are designed by using the Automatic Exhaustive Gate Designer.

enumerator RANDOM

Gate layouts are designed randomly.

enumerator PRUNING_ONLY

This design approach adopts the three pruning techniques used by QuickCell to efficiently filter out non-operational layouts. Unlike QuickCell, the subsequent physical simulation step is skipped to enhance efficiency. As a result, the operational validity of the final layouts cannot be guaranteed, although a substantial portion of them are usually operational.

Public Members

is_operational_params operational_params = {}

Parameters for the is_operational function.

design_sidb_gates_mode design_mode = design_sidb_gates_mode::AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER

Gate design mode.

std::pair<CellType, CellType> canvas = {{24, 17}, {34, 28}}

Canvas spanned by the northwest and southeast cell.

std::size_t number_of_canvas_sidbs = 1

Number of SiDBs placed in the canvas to create a working gate.

termination_condition termination_cond = termination_condition::AFTER_FIRST_SOLUTION

The design process is terminated after a valid SiDB gate design is found.

Note

This parameter has no effect unless the gate design is exhaustive.

template<typename Lyt, typename TT>
std::vector<Lyt> fiction::design_sidb_gates(const Lyt &skeleton, const std::vector<TT> &spec, const design_sidb_gates_params<cell<Lyt>> &params = {}, design_sidb_gates_stats *stats = nullptr) noexcept

The SiDB Gate Designer designs SiDB gate implementations based on a specified Boolean function, a skeleton layout (can hold defects), canvas size, and a predetermined number of canvas SiDBs. Three different design modes are implemented: quickcell, exhaustive and random design.

A first version of QuickCell was proposed in “Towards Fast Automatic Design of Silicon Dangling Bond Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in DATE 2025 (https://ieeexplore.ieee.org/abstract/document/10992885).

An extended version of QuickCell was proposed in “QuickCell: Fast Automatic Design of Standard Cells for Silicon Dangling Bond Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in TCAD 2025 (https://ieeexplore.ieee.org/document/11146893).

The Automatic Exhaustive Gate Designer was proposed in “Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds” by J. Drewniok, M. Walter, and R. Wille in NANOARCH 2023 (https://dl.acm.org/doi/10.1145/3611315.3633241).

The quickcell design mode consists of two key steps:

1. Initial Pruning: Efficient filtering techniques are applied to discard layouts that cannot correctly implement the specified logic.

2. Physical Simulation: The remaining candidate layouts undergo physical simulation to verify their operationality.

The exhaustive design is composed of three steps:

1. In the initial step, all possible distributions of number_of_canvas_sidbs SiDBs within a given canvas are exhaustively determined. This ensures exhaustive coverage of every potential arrangement of number_of_canvas_sidbs SiDBs across the canvas.

2. The calculated SiDB distributions are then incorporated into the skeleton, resulting in the generation of distinct SiDB layouts.

3. The generated SiDB layouts then undergo an extensive simulation process. All input combinations possible for the given Boolean function are used to verify if the logic is fulfilled.

The random design is composed of four steps:

1. A specified number of canvas SiDBs (number_of_canvas_sidbs) are randomly added to the skeleton layout.

2. The operation status of the layout is simulated based on a given Boolean function.

3. If the layout is operational, it is returned as the result, and the process terminates successfully.

4. If the layout is non-operational, the process is repeated from the first step until an operational layout is found.

Template Parameters:

• Lyt – SiDB cell-level layout type.

• TT – The type of the truth table specifying the gate behavior.

Parameters:

• skeleton – The skeleton layout used for gate design.

• spec – Expected Boolean function of the layout given as a multi-output truth table.

• params – Parameters for the SiDB Gate Designer.

• stats – Statistics.

Returns:

A vector of designed SiDB gate layouts.