SiDB Gate Designer

Header: fiction/algorithms/physical_design/design_sidb_gates.hpp

template<typename Lyt>
struct design_sidb_gates_params

This struct contains parameters and settings to design SiDB gates.

Template Parameters:

Cell-level – layout type.

Public Types

enum class design_sidb_gates_mode

Selector for the available design approaches.

Values:

enumerator EXHAUSTIVE

All gate layouts are designed exhaustively.

enumerator RANDOM

Gate layouts are designed randomly.

Public Members

sidb_simulation_parameters simulation_parameters = {}

All Parameters for physical SiDB simulations.

design_sidb_gates_mode design_mode = design_sidb_gates_mode::EXHAUSTIVE

Gate design mode.

std::pair<typename Lyt::cell, typename Lyt::cell> canvas = {}

Canvas spanned by the northwest and southeast cell.

std::size_t number_of_sidbs = 1

Number of SiDBs placed in the canvas to create a working gate.

sidb_simulation_engine sim_engine = {sidb_simulation_engine::QUICKEXACT}

The simulation engine to be used for the operational domain computation.

template<typename Lyt, typename TT>
std::vector<Lyt> fiction::design_sidb_gates(const Lyt &skeleton, const std::vector<TT> &spec, const design_sidb_gates_params<Lyt> &params = {}) noexcept

The SiDB Gate Designer designs SiDB gate implementations based on a specified Boolean function, a skeleton layout (can hold defects), canvas size, and a predetermined number of canvas SiDBs. Two different design modes are implemented: exhaustive and random design.

The exhaustive design is composed of three steps:

  1. In the initial step, all possible distributions of number_of_sidbs SiDBs within a given canvas are exhaustively determined. This ensures exhaustive coverage of every potential arrangement of number_of_sidbs SiDBs across the canvas.

  2. The calculated SiDB distributions are then incorporated into the skeleton, resulting in the generation of distinct SiDB layouts.

  3. The generated SiDB layouts then undergo an extensive simulation process. All input combinations possible for the given Boolean function are used to verify if the logic is fulfilled.

The random design is composed of four steps:

  1. A specified number of canvas SiDBs (number_of_sidbs) are randomly added to the skeleton layout.

  2. The operation status of the layout is simulated based on a given Boolean function.

  3. If the layout is operational, it is returned as the result, and the process terminates successfully.

  4. If the layout is non-operational, the process is repeated from the first step until an operational layout is found.

Template Parameters:

  • Lyt – SiDB cell-level layout type.

  • TT – The type of the truth table specifying the gate behavior.

Parameters:

  • skeleton – The skeleton layout used as a starting point for gate design.

  • spec – Expected Boolean function of the layout given as a multi-output truth table.

  • params – Parameters for the SiDB Gate Designer.

Returns:

A vector of designed SiDB gate layouts.