FCN Gate Libraries

A gate library is a set of cell-accurate implementations of gate functions. It breaks down each gate into a tile of cells. Thereby, via apply_gate_library, a gate_level_layout can be compiled down to a cell_level_layout of a concrete technology.

The implementation of a gate library should be non-instantiatable plus static and constexpr wherever possible. The abstract class fcn_gate_library provides utility functions that can be used to implement custom gate libraries by extending it.

Abstract Gate Library

Header: fiction/technology/fcn_gate_library.hpp

template<typename Technology, uint16_t GateSizeX, uint16_t GateSizeY> class fcn_gate_library

Base class for various FCN libraries used to map gate-level layouts to cell-level ones. Any new gate library can extend fcn_gate_library if it benefits from its features but does not have to. The only requirement is that it must be a static class that provides a

template <typename GateLyt>
static fcn_gate set_up_gate(const GateLyt& lyt, const tile<GateLyt>& t)

public member function. Additionally, a

template <typename CellLyt>
static void post_layout_optimization(CellLyt& lyt)

can optionally be provided if some cleanup or optimization is necessary on the cell-level layout after each gate has been mapped.

Additionally, a

static gate_functions get_functional_implementations()

can optionally be provided to allow reverse access to the gate structures by functional implementation. This interface is for example used to determine which gate types to blacklist on tiles in P&R algorithms by considering gate implementation.

Finally, a

static gate_ports<PortType> get_gate_ports()

can optionally be provided to allow reverse access to the gate ports given a gate implementation. This interface is for example used in sidb_surface_analysis to determine which ports to blacklist.

Template Parameters:

Technology – FCN technology type of the implementing gate library.
GateSizeX – Tile size in x-dimension.
GateSizeY – Tile size in y-dimension.

Public Types

template<typename T> using cell_list = std::array<std::array<T, GateSizeX>, GateSizeY>: A cell_list is an array of size GateSizeX \( \times \) GateSizeY of type T.

using fcn_gate = cell_list<typename Technology::cell_type>: Each gate is thus a cell_list of cell types defined in Technology.

using gate_functions = std::unordered_map<kitty::dynamic_truth_table, std::vector<fcn_gate>, kitty::hash<kitty::dynamic_truth_table>>: Maps truth tables to respective FCN gate implementations.

template<typename PortType> using gate_ports = std::unordered_map<fcn_gate, std::vector<port_list<PortType>>>: Maps FCN gate implementations to respective port lists indicating their possible orientations.

Public Functions

explicit fcn_gate_library() = delete: Gate libraries should not be instantiated but used as static objects.

Public Static Functions

template<typename T> static inline constexpr fcn_gate cell_list_to_gate(const cell_list<T> &c) noexcept

Converts a cell_list of type T to an fcn_gate at compile time. This function allows to conveniently specify fcn_gate instances in a semi-readable way in code. For examples usages see qca_one_library.hpp.

Template Parameters:: T – Element type of given cell_list.
Parameters:: c – Cell list to convert.
Returns:: An fcn_gate created from the representation provided in c.

static inline constexpr fcn_gate rotate_90(const fcn_gate &g) noexcept

Rotates the given fcn_gate by 90° clockwise at compile time.

Parameters:: g – fcn_gate to rotate.
Returns:: Rotated fcn_gate.

static inline constexpr fcn_gate rotate_180(const fcn_gate &g) noexcept

Rotates the given fcn_gate by 180° at compile time.

Parameters:: g – fcn_gate to rotate.
Returns:: Rotated fcn_gate.

static inline constexpr fcn_gate rotate_270(const fcn_gate &g) noexcept

Rotates the given fcn_gate by 270° clockwise at compile time.

Parameters:: g – fcn_gate to rotate.
Returns:: Rotated fcn_gate.

static inline constexpr fcn_gate merge(const std::vector<fcn_gate> &gates) noexcept

Merges multiple fcn_gates into one at compile time. This is intended to be used for wires. Unexpected behavior can be caused, if more than one fcn_gate has a cell at the same position.

Parameters:: gates – Vector of gates to be merged.
Returns:: Merged fcn_gate.

template<typename Port> static inline constexpr fcn_gate mark_cell(const fcn_gate &g, const Port &p, const typename Technology::cell_mark &mark) noexcept

Applies given mark to given fcn_gate g at given port p at compile time.

Parameters:

g – Gate to apply mark to.
p – Port specifying where to apply the mark.
mark – Mark to be applied

Returns:

Marked fcn_gate.

static inline constexpr uint16_t gate_x_size() noexcept

Returns horizontal size of gate blocks.

Returns:: GateSizeX.

static inline constexpr uint16_t gate_y_size() noexcept

Returns vertical size of gate blocks.

Returns:: GateSizeY.

template<typename CoordinateType> class unsupported_gate_type_exception : public std::exception

Exception to be thrown when a layout hosts a gate type that is not implemented in the applied gate library.

Template Parameters:: CoordinateType – Type of the layout coordinates.

template<typename CoordinateType, typename PortType> class unsupported_gate_orientation_exception : public std::exception

Exception to be thrown when a layout hosts a gate with an orientation that is unsupported by the applied gate library.

Template Parameters:

CoordinateType – Type of the layout coordinates.
PortType – Type of the library ports.

Header: fiction/technology/cell_ports.hpp

struct port_position

A port position is a relative location of a cell within a tile.

Public Functions

constexpr port_position() = default: Default constructor.

inline constexpr port_position(const uint16_t x_, const uint16_t y_, const bool pi_ = false, const bool po_ = false): Standard constructor.

inline constexpr bool operator<(const port_position &p) const

Comparator for set insertion.

Parameters:: p – Port to compare to.
Returns:: true iff this port goes before p in set.

inline constexpr bool operator==(const port_position &p) const

Comparator for equality tests.

Parameters:: p – Port to compare to.
Returns:: true iff this port is equal to given port p.

Public Members

uint16_t x = {}: Positions.

bool pi = false: Primary input port.

bool po = false: Primary output port.

struct port_direction

A port direction is a relative (cardinal) direction of a port within a tile. Useful, when no exact port locations within a tile are needed.

Public Types

enum cardinal

Cardinal direction.

Values:

enumerator NORTH

enumerator NORTH_EAST

enumerator EAST

enumerator SOUTH_EAST

enumerator SOUTH

enumerator SOUTH_WEST

enumerator WEST

enumerator NORTH_WEST

Public Functions

constexpr port_direction() = default: Default constructor.

inline explicit constexpr port_direction(const cardinal d, const bool pi_ = false, const bool po_ = false): Standard constructor.

inline constexpr bool operator<(const port_direction &p) const

Comparator for set insertion.

Parameters:: p – Port to compare to.
Returns:: true iff this port goes before p in set.

inline constexpr bool operator==(const port_direction &p) const

Comparator for equality tests.

Parameters:: p – Port to compare to.
Returns:: true iff this port is equal to given port p.

Public Members

uint8_t dir = {}: Direction.

bool pi = false: Primary input port.

bool po = false: Primary output port.

template<typename PortType> struct port_list

Port lists are collections of input and output ports.

Template Parameters:: PortType – A port type, e.g., port_position or port_direction.

Public Types

using port_type = PortType : Exposing the underlying port type.

Public Functions

constexpr port_list() = default: Default constructor.

inline port_list(std::set<PortType> input_ports, std::set<PortType> output_ports): Standard constructor.

inline bool operator==(const port_list<PortType> &p) const

Comparator for unordered_set/map.

Parameters:: p – Ports to compare to.
Returns:: true iff these ports are equal to p.

inline port_list<PortType> &operator+=(port_list<PortType> &p)

Merges two port_list objects together. The given port_list might be altered.

Parameters:: p – Ports to merge.
Returns:: Merged port lists.

Public Members

std::set<PortType> inp = {}: Input and output positions.

QCA ONE Library

Header: fiction/technology/qca_one_library.hpp

class qca_one_library : public fiction::fcn_gate_library<qca_technology, 5, 5>

A concrete FCN gate library based on QCA ONE proposed in “A Methodology for Standard Cell Design for QCA” by Dayane Alfenas Reis, Caio Araújo T. Campos, Thiago Rodrigues B. S. Soares, Omar Paranaiba V. Neto, and Frank Sill Torres in IEEE International Symposium on Circuits and Systems, 2016. QCA ONE was originally proposed for the USE clocking scheme. The version used here is an extension to the original QCA ONE by also theoretically allowing multiple wires in the same tile. Furthermore, it can be used for a range of clocking schemes. Tiles in QCA ONE are \( 5 \times 5 \) QCA cells.

Public Static Functions

template<typename GateLyt> static inline fcn_gate set_up_gate(const GateLyt &lyt, const tile<GateLyt> &t)

Overrides the corresponding function in fcn_gate_library. Given a tile t, this function takes all necessary information from the stored grid into account to choose the correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input and output, const cells etc. are computed additionally.

Template Parameters:

GateLyt – Cartesian gate-level layout type.

Parameters:

lyt – Layout that hosts tile t.
t – Tile to be realized as a QCA ONE gate.

Returns:

QCA ONE gate representation of t including I/Os, rotation, const cells, etc.

template<typename CellLyt> static inline void post_layout_optimization(CellLyt &lyt) noexcept

Post-layout optimization that assigns via cell mode to wire crossings.

Template Parameters:: CellLyt – Cell-level layout type.
Parameters:: lyt – The cell-level layout that has been created via application of set_up_gate.

iNML ToPoliNano Library

Header: fiction/technology/inml_topolinano_library.hpp

class inml_topolinano_library : public fiction::fcn_gate_library<inml_technology, 4, 4>

A concrete FCN gate library as used in “ToPoliNano” (https://topolinano.polito.it/) for the iNML technology. In fiction, this is emulated by using vertically shifted layouts and implementing the ToPoliNano library with \( 4 \times 4 \) magnet positions with one empty row in most tiles (except for MAJ which needs to be handled differently as this library is not uniform otherwise). Theoretically, it allows for multiple wires in the same tile.

Public Static Functions

template<typename GateLyt> static inline fcn_gate set_up_gate(const GateLyt &lyt, const tile<GateLyt> &t)

Overrides the corresponding function in fcn_gate_library. Given a tile t, this function takes all necessary information from the stored grid into account to choose the correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input and output, const cells etc. are computed additionally.

Template Parameters:

GateLyt – Shifted Cartesian gate-level layout type.

Parameters:

lyt – Layout that hosts tile t.
t – Tile to be realized as a ToPoliNano gate.

Returns:

ToPoliNano gate representation of t including I/Os, rotation, etc.

template<typename CellLyt> static inline void post_layout_optimization(CellLyt &lyt) noexcept

Post-layout optimization that straightens the wire segments to save cells.

Template Parameters:: CellLyt – Cell-level layout type.
Parameters:: lyt – The cell-level layout that has been created via application of set_up_gate.

SiDB Bestagon Library

Header: fiction/technology/sidb_bestagon_library.hpp

class sidb_bestagon_library : public fiction::fcn_gate_library<sidb_technology, 60, 46>

A gate library for the SiDB technology that is based on Y-shaped gates in hexagonal tiles. Y-shaped gates have been first introduced in “Binary Atomic Silicon Logic” by Taleana Huff, Hatem Labidi, Mohammad Rashidi, Lucian Livadaru, Thomas Dienel, Roshan Achal, Wyatt Vine, Jason Pitters, and Robert A. Wolkow in Nature Electronics 2018. The Bestagon library was later proposed in “Hexagons are the Bestagons: Design Automation for Silicon Dangling Bond Logic” by Marcel Walter, Samuel Sze Hang Ng, Konrad Walus, and Robert Wille in Design Automation Conference 2022. The goal of the Bestagon library is to be as close to physically realizable SiDB circuits as possible by taking fabrication limitations of, e.g., clocking electrodes into account while also relying on established gate shape. Thus, the hexagonal tiles in the Bestagon library are quite large with a lot of free space to avoid unwanted gate interactions. The Bestagon library is intended for hexagonal, pointy-top layouts that are clocked with a row-based clocking scheme, i.e., where the information flow direction is north to south.

Public Static Functions

template<typename GateLyt> static inline fcn_gate set_up_gate(const GateLyt &lyt, const tile<GateLyt> &t)

Overrides the corresponding function in fcn_gate_library. Given a tile t, this function takes all necessary information from the stored grid into account to choose the correct fcn_gate representation for that tile. May it be a gate or wires. Rotation and special marks like input and output, const cells etc. are computed additionally.

Template Parameters:

GateLyt – Pointy-top hexagonal gate-level layout type.

Parameters:

lyt – Layout that hosts tile t.
t – Tile to be realized as a Bestagon gate.

Returns:

Bestagon gate representation of t including mirroring.

static inline gate_functions get_functional_implementations() noexcept

Returns a map of all gate functions supported by the library and their respectively possible implementations.

This is an optional interface function that is required by some algorithms.

Returns:: Map of all gate functions supported by the library and their respective implementations as Bestagon gates.

static inline gate_ports<port_direction> get_gate_ports() noexcept

Returns a map of all different gate implementations and their respective port information.

This is an optional interface function that is required by some algorithms.

Returns:: Map of all different gate implementations and their respective port information.