SiDB Circuit Design Algorithm in the Presence of Atomic Defects

This algorithm is designed to create SiDB circuits on a clocked surface, accommodating the presence of atomic defects.

  1. Blacklist Generation:

    Initially, a blacklist of gate-tile pairs is generated. This blacklist is based on the locations of neutrally charged atomic defects and their overlap with the I/O pins of the SiDB skeletons.

  2. Gate-Level Layout Design:

    Using the generated blacklist, a gate-level layout is designed with the exact algorithm. This process involves:

    • Valid Layout Found:

      If a valid gate-level layout is found, the corresponding gates are implemented with SiDBs.

    • Invalid Layout:

      If a valid layout is not found, the blacklist is updated, and the placement and routing process is repeated.

This iterative approach ensures that the designed SiDB circuits can effectively handle defects present on the surface.

Header: fiction/algorithms/physical_design/on_the_fly_circuit_design.hpp

template<typename CellLyt>
struct on_the_fly_sidb_circuit_design_on_defective_surface_params

This struct stores the parameters to design an SiDB circuit on a defective surface.

Template Parameters:

CellLyt – SiDB cell-level layout type.

Public Members

sidb_on_the_fly_gate_library_params<CellLyt> sidb_on_the_fly_gate_library_parameters = {}

Parameters for the SiDB on-the-fly gate library.

exact_physical_design_params exact_design_parameters = {}

Parameters for the exact placement and routing algorithm.

template<typename CellLyt>
struct on_the_fly_sidb_circuit_design_params

This struct stores the parameters to design an SiDB circuit.

Template Parameters:

CellLyt – SiDB cell-level layout type.

Public Members

sidb_on_the_fly_gate_library_params<CellLyt> sidb_on_the_fly_gate_library_parameters = {}

Parameters for the SiDB on-the-fly gate library.

template<typename GateLyt>
struct on_the_fly_circuit_design_on_defective_surface_stats

Statistics for the on-the-fly defect-aware circuit design.

Template Parameters:

GateLyt – Gate-level layout type.

Public Members

mockturtle::stopwatch::duration time_total = {0}

The total runtime of the on-the-fly circuit design.

exact_physical_design_stats exact_stats = {}

The stats of the exact algorithm.

std::optional<GateLyt> gate_layout = {}

The gate-level layout after P&R.

template<typename Ntk, typename CellLyt, typename GateLyt>
CellLyt fiction::on_the_fly_sidb_circuit_design_on_defective_surface(const Ntk &ntk, const GateLyt &lattice_tiling, const CellLyt &defective_surface, const on_the_fly_sidb_circuit_design_on_defective_surface_params<cell<CellLyt>> &params = {}, on_the_fly_circuit_design_on_defective_surface_stats<GateLyt> *stats = nullptr)

This function implements an on-the-fly circuit design algorithm for a defective SiDB surface.

The process begins with placement and routing using a blacklist and the exact method. The blacklist includes skeleton-tile pairs that are excluded due to collisions between skeleton and neutral defects on specific tiles. After identifying a valid placement and routing, a defect-aware SiDB gate design algorithm is applied. This algorithm designs gates for each tile while accounting for atomic defects. If the gate design is unsuccessful, the blacklist is updated with the problematic skeleton-gate pair, and the placement and routing process is restarted. If the gate design succeeds, the algorithm finalizes the design and returns the SiDB circuit. This approach ensures that the circuit remains functional even in the presence of defects.

This methodology is detailed in the paper “On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond

Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024 (

https://ieeexplore.ieee.org/abstract/document/10628962).

Template Parameters:

  • Ntk – The type of the input network.

  • CellLyt – SiDB defect surface type.

  • GateLyt – Gate-level layout type.

Parameters:

  • ntk – The input network to be mapped onto the defective surface.

  • lattice_tiling – The lattice tiling used for the circuit design.

  • defective_surface – The defective surface on which the SiDB circuit is designed.

  • params – The parameters used for designing the circuit, encapsulated in an on_the_fly_sidb_circuit_design_params object.

  • stats – Pointer to a structure for collecting statistics. If nullptr, statistics are discarded.

Returns:

Layout representing the designed circuit on the defective surface.

template<typename CellLyt, typename GateLyt>
CellLyt fiction::on_the_fly_sidb_circuit_design(const GateLyt &gate_lyt, const on_the_fly_sidb_circuit_design_params<CellLyt> &params = {})

This function implements an on-the-fly SiDB circuit design algorithm.

The process begins with an already placed and routed gate-level layout. For each gate, the corresponding SiDB implementation is designed by using an SiDB gate design algorithm.

Template Parameters:

  • CellLyt – SiDB cell-level layout type.

  • GateLyt – Gate-level layout type.

Parameters:

  • gate_lyt – Gate-level layout.

  • lattice_tiling – The lattice tiling used for the circuit design.

  • params – The parameters used for designing the circuit, encapsulated in an on_the_fly_sidb_circuit_design_params object.

  • stats – Pointer to a structure for collecting statistics. If nullptr, statistics are discarded.

Returns:

Layout representing the designed SiDB circuit.