Optimizing 2DDWave-clocked Cartesian Layouts

This algorithm aims to decrease the overall layout area of a given 2DDWave-clocked Cartesian layout that has been generated using either heuristic methods or machine learning techniques. It achieves this objective by strategically repositioning gates within the layout, removing excess wiring using the wiring_reduction algorithm (cf. Wiring Reduction in 2DDWave-clocked Cartesian Layouts), and effectively relocating outputs to more favorable positions.

Header: fiction/algorithms/physical_design/post_layout_optimization.hpp

struct post_layout_optimization_params

Parameters for the post-layout optimization algorithm.

Public Members

std::optional<uint64_t> max_gate_relocations = std::nullopt

Maximum number of relocations to try for each gate. Defaults to the number of tiles in the given layout if not specified.

bool optimize_pos_only = false

Only optimize PO positions.

bool planar_optimization = false

Disable the creation of crossings during optimization. If set to true, gates will only be relocated if a crossing-free wiring is found. Defaults to false.

uint64_t timeout = std::numeric_limits<uint64_t>::max()

Timeout limit (in ms). Specifies the maximum allowed time in milliseconds for the optimization process. For large layouts, the actual execution time may slightly exceed this limit because it’s impractical to check the timeout at every algorithm step and the functional correctness has to be ensured by completing essential algorithm steps.

struct post_layout_optimization_stats

This struct stores statistics about the post-layout optimization process.

Public Functions

inline void report(std::ostream &out = std::cout) const

Reports the statistics to the given output stream.

Parameters:

out – Output stream.

Public Members

mockturtle::stopwatch::duration time_total = {0}

Runtime of the post-layout optimization process.

uint64_t x_size_before = {0ull}

Layout width before the post-layout optimization process.

uint64_t y_size_before = {0ull}

Layout height before the post-layout optimization process.

uint64_t x_size_after = {0ull}

Layout width after the post-layout optimization process.

uint64_t y_size_after = {0ull}

Layout height after the post-layout optimization process.

double_t area_improvement = {0ull}

Area reduction (in %) after the post-layout optimization process.

uint64_t num_wires_before = {0ull}

Number of wire segments before the post-layout optimization process.

uint64_t num_wires_after = {0ull}

Number of wire segments after the post-layout optimization process.

uint64_t num_crossings_before = {0ull}

Number of crossings before the post-layout optimization process.

uint64_t num_crossings_after = {0ull}

Number of crossings after the post-layout optimization process.

template<typename Lyt>
void fiction::post_layout_optimization(const Lyt &lyt, post_layout_optimization_params ps = {}, post_layout_optimization_stats *pst = nullptr) noexcept

A post-layout optimization algorithm as originally proposed in “Post-Layout Optimization for Field-coupled Nanotechnologies” by S. Hofmann, M. Walter, and R. Wille in NANOARCH 2023 (https://dl.acm.org/doi/10.1145/3611315.3633247) and extended in “Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies” by S. Hofmann, M. Walter, and R. Wille in TCAD 2025 (https://ieeexplore.ieee.org/document/10916761). It can be used to reduce the area of a given sub-optimal Cartesian gate-level layout created by heuristics or machine learning. This optimization utilizes the distinct characteristics of the 2DDWave clocking scheme, which only allows information flow from top to bottom and left to right, therefore only aforementioned clocking scheme is supported.

To reduce the layout area, first, gates are moved up and to the left as far as possible, including rerouting. This creates more compact layouts by freeing up space to the right and bottom, as all gates were moved to the top left corner.

After moving all gates, this algorithm also checks if excess wiring exists on the layout using the wiring_reduction algorithm (cf. wiring_reduction.hpp)

As outputs have to lay on the border of a layout for better accessibility, they are also moved to new borders determined based on the location of all other gates.

Note

This function requires the gate-level layout to be 2DDWave-clocked!

Template Parameters:

Lyt – Cartesian gate-level layout type.

Parameters:

  • lyt – 2DDWave-clocked Cartesian gate-level layout to optimize.

  • ps – Parameters.

  • pst – Statistics.