Optimizing 2DDWave-clocked Cartesian Layouts

This algorithm aims to decrease the overall layout area of a given 2DDWave-clocked Cartesian layout that has been generated using either heuristic methods or machine learning techniques. It achieves this objective by strategically repositioning gates within the layout, removing excess wiring, and effectively relocating outputs to more favorable positions.

Header: fiction/algorithms/physical_design/post_layout_optimization.hpp

struct post_layout_optimization_stats

This struct stores statistics about the post-layout optimization process.

Public Functions

inline void report(std::ostream &out = std::cout) const

Reports the statistics to the given output stream.

Parameters:: out – Output stream.

Public Members

mockturtle::stopwatch::duration time_total = {0}: Runtime of the post-layout optimization process.

template<typename Lyt> void fiction::post_layout_optimization(const Lyt &lyt, post_layout_optimization_stats *pst = nullptr) noexcept

A post-layout optimization algorithm as originally proposed in “Post-Layout Optimization for Field-coupled Nanotechnologies” by S. Hofmann, M. Walter, and R. Wille in NANOARCH 2023. It can be used to reduce the area of a given sub-optimal Cartesian gate-level layout created by heuristics or machine learning. This optimization utilizes the distinct characteristics of the 2DDWave clocking scheme, which only allows information flow from top to bottom and left to right, therefore only aforementioned clocking scheme is supported.

To reduce the layout area, first, gates are moved up and to the left as far as possible, including rerouting. This creates more compact layouts by freeing up space to the right and bottom, as all gates were moved to the top left corner.

After moving all gates, this algorithm also checks if excess wiring exists on the layout, i.e., rows that only contain vertical wires or columns that only contain horizontal wires and removes them.

As outputs have to lay on the border of a layout for better accessibility, they are also moved to new borders determined based on the location of all other gates.

Note

This function requires the gate-level layout to be 2DDWave-clocked!

Template Parameters:: Lyt – Cartesian gate-level layout type.
Parameters:: lyt – 2DDWave-clocked Cartesian gate-level layout to optimize.

class mnt.pyfiction.post_layout_optimization_stats: This struct stores statistics about the post-layout optimization process.

mnt.pyfiction.post_layout_optimization(lyt: mnt.pyfiction.cartesian_gate_layout, pst: mnt.pyfiction.post_layout_optimization_stats = None) → None

A post-layout optimization algorithm as originally proposed in "Post- Layout Optimization for Field-coupled Nanotechnologies" by S. Hofmann, M. Walter, and R. Wille in NANOARCH 2023. It can be used to reduce the area of a given sub-optimal Cartesian gate-level layout created by heuristics or machine learning. This optimization utilizes the distinct characteristics of the 2DDWave clocking scheme, which only allows information flow from top to bottom and left to right, therefore only aforementioned clocking scheme is supported.

To reduce the layout area, first, gates are moved up and to the left as far as possible, including rerouting. This creates more compact layouts by freeing up space to the right and bottom, as all gates were moved to the top left corner.

After moving all gates, this algorithm also checks if excess wiring exists on the layout, i.e., rows that only contain vertical wires or columns that only contain horizontal wires and removes them.

As outputs have to lay on the border of a layout for better accessibility, they are also moved to new borders determined based on the location of all other gates.

@note This function requires the gate-level layout to be 2DDWave- clocked!

Template parameter Lyt:: Cartesian gate-level layout type.
Parameter lyt:: 2DDWave-clocked Cartesian gate-level layout to optimize.