Let there be a fiction

• What is this about?
• Getting started
  • Compilation requirements
  • Using fiction as a stand-alone CLI tool
  • Using fiction as a header-only library
  • Python Bindings
  • Enabling dependent functions
  • Building experiments
  • Building tests
  • Building code benchmarks
  • Noteworthy CMake options
  • Uninstall
• Command Line Interface (CLI)
  • Preface
  • Stores
  • Circuit specifications
  • ABC Callback
  • Physical design
  • Design rule checking (check)
  • Logical simulation (simulate)
  • Equivalence checking (equiv)
  • Energy dissipation (energy)
  • Physical synthesis (cell)
  • Physical Simulation of SiDBs
  • Area usage (area)
  • SVG export (show -c)
  • Benchmarking and scripting
• Changelog
  • v0.6.10 - 2025-02-21
  • v0.6.9 - 2025-02-12
  • v0.6.8 - 2025-01-25
  • v0.6.7 - 2025-01-20
  • v0.6.6 - 2024-11-26
  • v0.6.5 - 2024-10-22
  • v0.6.4 - 2024-08-30
  • v0.6.3 - 2024-08-22
  • v0.6.2 - 2024-05-22
  • v0.6.1 - 2024-05-16
  • v0.6.0 - 2024-05-05
  • v0.5.0 - 2023-03-30
  • v0.4.0 - 2022-01-27
  • v0.3.2 - 2021-01-06
  • v0.3.1 - 2020-06-04
  • v0.3.0 - 2019-11-22
  • v0.2.1 - 2019-05-02
  • v0.2.0 - 2019-03-21
  • v0.1.1 - 2018-12-29
  • v0.1.0 - 2018-10-29
• Publications
• Acknowledgments
• Contributing
  • Types of Contributions
  • First Contributions
  • Core Guidelines
  • Pull Request Workflow
• Support

Networks

• Technology Network
  • technology_network
  • technology_network
• Views
  • Edge Color View
  • Static Depth View
  • Mutable Rank View

Layouts

• Coordinate Systems
  • Offset coordinates
  • Cube coordinates
  • SiQAD coordinates
  • Coordinate iterator
  • Utility functions
• Cartesian Layout
  • cartesian_layout
  • cartesian_layout
• Shifted Cartesian Layout
  • horizontal_shift_cartesian
  • vertical_shift_cartesian
  • odd_row_cartesian
  • even_row_cartesian
  • odd_column_cartesian
  • even_column_cartesian
  • shifted_cartesian_layout
  • shifted_cartesian_layout
• Hexagonal Layout
  • pointy_top_hex
  • flat_top_hex
  • odd_row_hex
  • even_row_hex
  • odd_column_hex
  • even_column_hex
  • hexagonal_layout
  • hexagonal_layout
• Tile-based Layout
  • tile_based_layout
• Clocked Layout
  • clocked_layout
  • clocked_cartesian_layout
  • clocked_hexagonal_layout
• Clocking Schemes
  • clocking_scheme
  • Pre-defined schemes
  • Utility functions
• Synchronization Element Layout
  • synchronization_element_layout
• Gate-level Layout
  • gate_level_layout
  • cartesian_gate_layout
  • hexagonal_gate_layout
• Cell-level Layout
  • cell_level_layout
  • qca_layout
  • inml_layout
  • sidb_layout
• Obstruction Layout
  • obstruction_layout
  • obstruction_layout
  • obstruction_layout
  • cartesian_obstruction_layout
  • shifted_cartesian_obstruction_layout
  • hexagonal_obstruction_layout
• Bounding Box
  • bounding_box_2d
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()
  • bounding_box_2d()

Algorithms

• Iterators
  • Aspect Ratio Iterator
  • Gray Code Iterator
  • BDL Input Iterator
• Path Finding
  • Distance Functions
  • Distance Maps
  • Cost Functions
  • A* Shortest Path
  • Jump Point Search Shortest Path in a Cartesian Grid
  • k Shortest Paths
  • Enumerate All Paths
• Graph Algorithms
  • Generate Edge Intersection Graph
  • Graph Coloring
• Optimization
  • Simulated Annealing
• Network Transformation
  • Network Conversion
  • Network Balancing
  • Fanout Substitution
  • Technology Mapping
  • Delete Virtual PIs
• Physical Design
  • SMT-based Exact Physical Design
  • Scalable Orthogonal Physical Design
  • Graph-oriented Layout Design
  • SAT-based One-pass Synthesis
  • Multi-Path Routing (Color Routing)
  • Mapping Cartesian to Hexagonal Layouts
  • Optimizing 2DDWave-clocked Cartesian Layouts
  • Wiring Reduction in 2DDWave-clocked Cartesian Layouts
  • Determine Clocking
  • Apply Gate Library
  • SiDB Gate Designer
  • SiDB Circuit Design Algorithm in the Presence of Atomic Defects
• Verification
  • Design Rule Violations (DRVs)
  • Equivalence Checking
  • Virtual Miter
• Simulation
  • Physical Simulation of Silicon Dangling Bond Logic
• Properties
  • Critical Path (CP) and Throughput (TP)
  • Number of Gate Types

Technology

• FCN Cell Technologies
  • Quantum-dot Cellular Automata (QCA)
  • in-plane Nanomagnet Logic (iNML)
  • Silicon Dangling Bonds (SiDB)
• H-Si Lattice Orientations
  • sidb_100_lattice
  • sidb_111_lattice
  • sidb_100_lattice
  • sidb_111_lattice
• SiDB Lattice Layout
  • sidb_lattice
  • sidb_100_lattice
  • sidb_111_lattice
• Fabrication Defects
  • SiDB Defect Types
  • SiDB Defect Surface
  • SiDB Defect Analysis
• Physical Simulation of SiDBs
  • SiDB Charge States
  • SiDB Charge Distribution Surface
  • Is SiDB gate design deemed impossible
  • Physical Constants
  • Euclidean distance between two SiDBs in nanometers
  • SiDB Cluster Hierarchy
• FCN Gate Libraries
  • Abstract Gate Library
  • QCA ONE Library
  • iNML ToPoliNano Library
  • SiDB Bestagon Library
  • Parameterized SiDB Library

Input/Output

• Input Parsing
  • Logic Networks
  • Truth Tables
  • Gate-level Layouts
  • Cell-level Layouts
  • SiDB Surface Defects
• Visualization
  • Layout Printing
  • Graphviz (DOT) Drawers
  • SVG Images
• Physical Simulation
  • QCADesigner
  • QCA-STACK
  • ToPoliNano
  • MagCAD & SCERPA
  • SiQAD
  • SiDB Operational Domain
  • Technology-independent Gate-level Layouts
• Utility
  • csv_writer

Utility

• Network Utils
  • edge
  • foreach_edge()
  • foreach_outgoing_edge()
  • foreach_incoming_edge()
  • fanouts()
  • fanin_container
  • fanins()
  • num_constant_fanins()
  • high_degree_fanin_exception
  • has_high_degree_fanin_nodes()
  • fanin_edge_container
  • fanin_edges()
  • has_incoming_primary_input()
  • all_incoming_edge_paths()
  • inverse_levels()
  • high_degree_fanin_exception
  • has_high_degree_fanin_nodes()
• Truth Table Utils
  • create_id_tt()
  • create_not_tt()
  • create_and_tt()
  • create_or_tt()
  • create_nand_tt()
  • create_nor_tt()
  • create_xor_tt()
  • create_xnor_tt()
  • create_lt_tt()
  • create_gt_tt()
  • create_le_tt()
  • create_ge_tt()
  • create_and3_tt()
  • create_xor_and_tt()
  • create_or_and_tt()
  • create_onehot_tt()
  • create_maj_tt()
  • create_gamble_tt()
  • create_dot_tt()
  • create_ite_tt()
  • create_and_xor_tt()
  • create_xor3_tt()
  • create_double_wire_tt()
  • create_crossing_wire_tt()
  • create_fan_out_tt()
  • create_half_adder_tt()
  • create_id_tt()
  • create_not_tt()
  • create_and_tt()
  • create_or_tt()
  • create_nand_tt()
  • create_nor_tt()
  • create_xor_tt()
  • create_xnor_tt()
  • create_lt_tt()
  • create_gt_tt()
  • create_le_tt()
  • create_ge_tt()
  • create_and3_tt()
  • create_xor_and_tt()
  • create_or_and_tt()
  • create_onehot_tt()
  • create_maj_tt()
  • create_gamble_tt()
  • create_dot_tt()
  • create_ite_tt()
  • create_and_xor_tt()
  • create_xor3_tt()
  • create_double_wire_tt()
  • create_crossing_wire_tt()
  • create_fan_out_tt()
  • create_half_adder_tt()
• Layout Utils
  • num_adjacent_coordinates()
  • relative_to_absolute_cell_position()
  • port_direction_to_coordinate()
  • normalize_layout_coordinates()
  • convert_layout_to_siqad_coordinates()
  • convert_layout_to_fiction_coordinates()
  • random_coordinate()
  • all_coordinates_in_spanned_area()
  • num_adjacent_coordinates()
  • normalize_layout_coordinates()
  • convert_layout_to_siqad_coordinates()
  • random_coordinate()
• Placement Utils
  • reserve_input_nodes()
  • place()
  • place()
  • place()
  • place()
  • place()
  • branching_signal_container
  • place()
  • reserve_input_nodes()
  • place()
• Routing Utils
  • routing_objective
  • layout_coordinate_path
  • path_collection
  • path_set
  • is_crossable_wire()
  • route_path()
  • extract_routing_objectives()
  • clear_routing()
  • is_crossable_wire()
  • route_path()
  • extract_routing_objectives()
  • clear_routing()
• Name Utils
  • get_name()
  • set_name()
  • restore_network_name()
  • restore_input_names()
  • restore_output_names()
  • restore_signal_names()
  • restore_signal_names()
  • restore_names()
  • restore_names()
  • get_name()
  • set_name()
• Array Utils
  • create_array()
  • convert_array()
  • convert_array_of_arrays()
• STL Extensions
  • find_first_two_of()
  • searchable_priority_queue
• Execution Policy Macros
• Ranges
  • range_t
• Hashing
  • hash_combine()
• Math Utils
  • round_to_n_decimal_places()
  • integral_abs()
  • binomial_coefficient()
  • determine_all_combinations_of_distributing_k_entities_on_n_positions()
  • cartesian_combinations()
• phmap
  • locked_parallel_flat_hash_map