Let there be a fiction

• What is this about?
• Getting started
  • Compilation requirements
  • Using fiction as a stand-alone CLI tool
  • Using fiction as a header-only library
  • Enabling dependent functions
  • Building tests
  • Building experiments
  • Uninstall
• Command Line Interface (CLI)
  • Preface
  • Stores
  • Circuit specifications
  • Physical design
  • Design rule checking (check)
  • Logical simulation (simulate)
  • Equivalence checking (equiv)
  • Energy dissipation (energy)
  • Physical synthesis (cell)
  • Area usage (area)
  • SVG export (show -c)
  • Benchmarking and scripting
• Changelog
  • v0.5.0 - 2023-03-30
  • v0.4.0 - 2022-01-27
  • v0.3.2 - 2021-01-06
  • v0.3.1 - 2020-06-04
  • v0.3.0 - 2019-11-22
  • v0.2.1 - 2019-05-02
  • v0.2.0 - 2019-03-21
  • v0.1.1 - 2018-12-29
  • v0.1.0 - 2018-10-29
• Publications
• Acknowledgments
• Contributing
  • Types of Contributions
  • 🎉 Getting Started
  • Core Guidelines
  • Pull Request Workflow
• Support

Networks

• Technology Network
• Views
  • Edge Color View

Layouts

• Coordinate Systems
  • Offset coordinates
  • Cube coordinates
  • SiQAD coordinates
  • Coordinate iterator
  • Utility functions
• Cartesian Layout
• Shifted Cartesian Layout
• Hexagonal Layout
• Tile-based Layout
• Clocked Layout
• Clocking Schemes
  • Pre-defined schemes
  • Utility functions
• Synchronization Element Layout
• Gate-level Layout
• Cell-level Layout
• Obstruction Layout
• Bounding Box

Algorithms

• Iterators
  • Aspect Ratio Iterator
• Path Finding
  • Distance Functions
  • Cost Functions
  • A* Shortest Path
  • Jump Point Search Shortest Path in a Cartesian Grid
  • k Shortest Paths
  • Enumerate All Paths
• Graph Algorithms
  • Generate Edge Intersection Graph
  • Graph Coloring
• Optimization
  • Simulated Annealing
• Network Transformation
  • Network Conversion
  • Network Balancing
  • Fanout Substitution
• Physical Design
  • SMT-based Exact Physical Design
  • Scalable Orthogonal Physical Design
  • SAT-based One-pass Synthesis
  • Multi-Path Routing (Color Routing)
  • Apply Gate Library
  • Mapping Cartesian to Hexagonal Layouts
• Verification
  • Design Rule Violations (DRVs)
  • Equivalence Checking
• Simulation
  • SiDB Electrostatic Ground State Simulation
• Properties
  • Critical Path (CP) and Throughput (TP)
  • Number of Gate Types

Technology

• FCN Cell Technologies
  • Quantum-dot Cellular Automata (QCA)
  • in-plane Nanomagnet Logic (iNML)
  • Silicon Dangling Bonds (SiDB)
• Fabrication Defects
  • SiDB Defect Types
  • SiDB Defect Surface
  • SiDB Defect Analysis
• Physical Simulation of SiDBs
  • SiDB Charge States
  • SiDB Charge Distribution Surface
• FCN Gate Libraries
  • Abstract Gate Library
  • QCA ONE Library
  • iNML ToPoliNano Library
  • SiDB Bestagon Library
• Physical Properties
  • Area Requirements
  • MagCAD Magnet Count

Input/Output

• Input Parsing
  • Logic Networks
  • Truth Tables
  • Cell-level Layouts
  • SiDB Surface Defects
• Visualization
  • Layout Printing
  • Graphviz (DOT) Drawers
  • SVG Images
• Physical Simulation
  • QCADesigner
  • QCA-STACK
  • ToPoliNano
  • MagCAD & SCERPA
  • SiQAD

Utility

• Network Utils
• Truth Table Utils
• Layout Utils
• Placement Utils
• Routing Utils
• Name Utils
• Array Utils
• STL Extensions
• Execution Policy Macros
• Ranges
• Hashing