Mapping Cartesian to Hexagonal Layouts
This algorithm maps Cartesian 2DDWave-clocked layouts used for Quantum-dot Cellular Automata (QCA) to hexagonal row-clocked layouts, which are suitable for Silicon Dangling Bonds (SiDBs).
The respective coordinates on the hexagonal grid are calculated as follows:
Header: fiction/algorithms/physical_design/hexagonalization.hpp
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struct hexagonalization_stats
This struct stores statistics about the hexagonalization process.
Public Functions
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inline void report(std::ostream &out = std::cout) const
Reports the statistics to the given output stream.
- Parameters:
out – Output stream.
Public Members
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mockturtle::stopwatch::duration time_total = {0}
Runtime of the hexagonalization process.
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inline void report(std::ostream &out = std::cout) const
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template<typename HexLyt, typename CartLyt>
HexLyt fiction::hexagonalization(const CartLyt &lyt, hexagonalization_stats *pst = nullptr) noexcept Transforms a 2DDWave-clocked Cartesian layout into a hexagonal even row clocked layout suitable for SiDBs by remapping all gates and wires as originally proposed in “Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel” by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2023 (https://ieeexplore.ieee.org/document/10231278).
- Template Parameters:
HexLyt – Even-row hexagonal gate-level layout return type.
CartLyt – Input Cartesian gate-level layout type.
- Parameters:
lyt – 2DDWave-clocked Cartesian gate-level layout to hexagonalize.
- Returns:
Hexagonal representation of the Cartesian layout.
- mnt.pyfiction.hexagonalization(layout: mnt.pyfiction.cartesian_gate_layout) mnt.pyfiction.hexagonal_gate_layout
Transforms a 2DDWave-clocked Cartesian layout into a hexagonal even row clocked layout suitable for SiDBs by remapping all gates and wires as originally proposed in "Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel" by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2023 (https://ieeexplore.ieee.org/document/10231278).
- Template parameter
HexLyt
: Even-row hexagonal gate-level layout return type.
- Template parameter
CartLyt
: Input Cartesian gate-level layout type.
- Parameter
lyt
: 2DDWave-clocked Cartesian gate-level layout to hexagonalize.
- Returns:
Hexagonal representation of the Cartesian layout.
- Template parameter