Mapping Cartesian to Hexagonal Layouts

This algorithm maps Cartesian 2DDWave-clocked layouts used for Quantum-dot Cellular Automata (QCA) to hexagonal row-clocked layouts, which are suitable for Silicon Dangling Bonds (SiDBs).

The respective coordinates on the hexagonal grid are calculated as follows:

\[y_{\mathit{hex}} = x_{\mathit{Cart}} + y_{\mathit{Cart}}\]

\[x_{\mathit{hex}} = x_{\mathit{Cart}} + \left \lceil{\left \lfloor{\frac{h}{2}} \right \rfloor} - \frac{y_{\mathit{hex}}}{2}\right \rceil\]

C++Python

Header: fiction/algorithms/physical_design/hexagonalization.hpp

struct hexagonalization_params

This structure encapsulates settings that determine how primary inputs (PIs) and primary outputs (POs) are handled during the conversion from a Cartesian to a hexagonal layout.

Public Types

enum io_pin_extension_mode

Specifies how primary inputs/outputs should be handled in the hexagonalization process.

Values:

enumerator NONE

Do not extend primary inputs/outputs to the top/bottom row (default).

enumerator EXTEND

Extend primary inputs/outputs to the top/bottom row.

enumerator EXTEND_PLANAR

Extend primary inputs/outputs to the top/bottom row with planar rerouting (i.e., without crossings).

Public Members

io_pin_extension_mode input_pin_extension = NONE

Input extension mode. Defaults to none

io_pin_extension_mode output_pin_extension = NONE

Output extension mode. Defaults to none

struct hexagonalization_stats

This struct stores statistics about the hexagonalization process.

Public Functions

inline void report(std::ostream &out = std::cout) const

Reports the statistics to the given output stream.

Parameters:

out – Output stream.

Public Members

mockturtle::stopwatch::duration time_total = {0}

Runtime of the hexagonalization process.

template<typename HexLyt, typename CartLyt>
HexLyt fiction::hexagonalization(const CartLyt &lyt, const hexagonalization_params &params = {}, hexagonalization_stats *stats = nullptr)

Transforms a 2DDWave-clocked Cartesian layout into a hexagonal even row clocked layout suitable for SiDBs by remapping all gates and wires as originally proposed in “Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel” by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2023 (https://ieeexplore.ieee.org/document/10231278).

Template Parameters:

• HexLyt – Even-row hexagonal gate-level layout return type.

• CartLyt – Input Cartesian gate-level layout type.

Parameters:

• lyt – 2DDWave-clocked Cartesian gate-level layout to hexagonalize.

• params – Parameters.

• stats – Statistics.

Returns:

Hexagonal representation of the Cartesian layout.