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fiction 0.8.1.dev169 documentation
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fiction 0.8.1.dev169 documentation

User Guide

  • What is this about?
  • Getting started
  • Command Line Interface (CLI)
  • Publications
  • Changelog
  • Acknowledgments

API Reference

  • Layouts
    • Bounding Box
    • Cartesian Layout
    • Cell Grids and Tile Clocking
    • Clocking Schemes
    • Clocking State
    • Coordinates
    • Gate-Level Layout
    • Hexagonal Layout
    • Obstructions
    • Shifted Cartesian Layout
    • Layout I/O
      • Gate-Level Layouts
      • Technology-Independent Gate-Level Layouts
      • Layout Printing
      • Graphviz (DOT) Drawers
    • Layout Utilities
    • Type Traits
    • Preset Types
  • Networks
    • Technology Network
    • Virtual PI Network
    • Network I/O
      • Logic Networks
      • Graphviz (DOT) Drawers
      • Network Writers
    • Views
      • Breadth-First Topological View (bfs_topo_view)
      • Edge Color View
      • Static Depth View
      • Mutable Rank View
    • Network Utilities
    • Name Utilities
    • Simulation and Random Generation
    • Interface Matching
    • Layout Network Extraction
  • Synthesis
    • Network Transformation
    • Synthesis I/O
      • Truth Tables
    • Technology Mapping Options
  • Physical Design
    • Apply Gate Library
    • Multi-Path Routing (Color Routing)
    • Determine Clocking
    • SMT-Based Exact Physical Design
    • Graph-Oriented Layout Design
    • Mapping Cartesian to Hexagonal Layouts
    • Scalable Orthogonal Physical Design
    • Optimizing 2DDWave-Clocked Cartesian Layouts
    • Surface Analysis
    • Wiring Reduction in 2DDWave-Clocked Cartesian Layouts
    • Path Finding
      • Path Finding Example
      • Distance Functions
      • Distance Maps
      • Cost Functions
      • A* Shortest Path
      • k Shortest Paths
      • Enumerate All Paths
    • Generate Edge Intersection Graph
    • Aspect Ratio Iterator
    • Placement Utilities
    • Routing Utilities
  • Verification
    • Layout Properties
    • Design Rule Violations (DRVs)
    • Equivalence Checking
    • Virtual Miter
  • Technologies
    • FCN
      • FCN I/O
        • MagCAD & SCERPA
        • Unsupported Cell Types
      • Abstract Gate Library
      • Area Requirements
    • QCA
      • QCA I/O
        • QCADesigner
        • SVG Images
      • QCA Layout
      • QCA ONE Library
    • molQCA
      • molQCA I/O
        • SVG Images
      • molQCA Layout
      • SIM(7) Library
    • iNML
      • iNML I/O
        • ToPoliNano
      • iNML Layout
      • iNML ToPoliNano Library
      • MagCAD Magnet Count
    • SiDB
      • Generators
        • SiDB Gate Designer
        • On-the-Fly SiDB Circuit Design
        • Random SiDB Layout Generator
        • Gate Design Feasibility
      • I/O
        • Dot Layouts
        • SiDB Surface Defects
        • SiQAD
        • SVG Images
        • Layout Printing
      • Layout
      • Model
        • Physical Parameters
        • Convert Potential to Distance
        • SiDB Defect Types
        • SiDB Charge States
        • Physical Constants
      • Simulation
        • Analysis
          • Energy Calculation
          • Temperature Behavior
          • Time-to-Solution (TTS) Statistics
          • Physically Valid Parameters
          • Charge Detection
          • Assess Population Stability
          • Band-Bending Resilience
        • Defects
          • Displacement Robustness Domain
          • Defect Influence
        • Engines
          • Heuristic Ground State Simulation
          • Exhaustive Ground State Simulation
          • Ground State Space Construction
          • Simulation Engine Example
        • I/O
          • SiDB Operational Domain
          • SiQAD Simulation Results
          • Defect Influence Domain
        • Logic
          • BDL Input Iterator
          • Operational Checks
          • Operational Domain Computation
          • Operational Domain Ratio
          • Logic Matching
          • Binary-Dot Logic (BDL) Pair Detection
          • Binary-Dot Logic (BDL) Wire Detection
          • Logic Simulation Example
        • Timeouts
        • Simulation Result
        • Potential Landscape
        • Engine Selectors
        • Simulation Equivalence Checking
        • Ground State Check
        • Simulation Domain
      • SiDB Bestagon Library
      • Parameterized SiDB Library
      • Skeleton Bestagon Library
  • Utilities
    • Math Utilities
      • Gray Code Iterator
      • Map Utilities
      • Arithmetic
      • Combinations
    • STL Utilities
      • Array Utilities
      • STL Extensions
      • Hashing
      • phmap
    • Graph Algorithms
      • Crossing Minimization (MinCross)
      • Graph Coloring
    • Optimization
      • Simulated Annealing
    • I/O
      • CSV Writer
    • Progress Reporting
    • Execution Deadlines

Development

  • Contributing
  • Tooling
  • Support
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Technology Mapping Options¶

class TechnologyMappingOptions[source]¶

Complete boolean keyword dictionary returned by gate-set factories.

decay: bool¶
inv: bool¶
and2: bool¶
nand2: bool¶
or2: bool¶
nor2: bool¶
xor2: bool¶
xnor2: bool¶
lt2: bool¶
gt2: bool¶
le2: bool¶
ge2: bool¶
and3: bool¶
xor_and: bool¶
or_and: bool¶
onehot: bool¶
maj3: bool¶
gamble: bool¶
dot: bool¶
mux: bool¶
and_xor: bool¶

The Munich Nanotech Toolkit has been supported by the Bavarian State Ministry for Science and Arts through the Distinguished Professorship Program.

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Copyright © 2018-2023: Marcel Walter. 2023-present: Chair for Design Automation, TUM
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On this page
  • Technology Mapping Options
    • TechnologyMappingOptions
      • decay
      • inv
      • and2
      • nand2
      • or2
      • nor2
      • xor2
      • xnor2
      • lt2
      • gt2
      • le2
      • ge2
      • and3
      • xor_and
      • or_and
      • onehot
      • maj3
      • gamble
      • dot
      • mux
      • and_xor