Network Writers

write_verilog(network: technology_network, filename: str) → None

write_verilog(network: aig_network, filename: str) → None

write_verilog(network: xag_network, filename: str) → None

write_verilog(network: mig_network, filename: str) → None

Writes the network as a gate-level Verilog file whose module is named top, as the readers expect. A technology network is written as an equivalent XAG, because gate-level Verilog has no buffers or fan-out nodes. A file that cannot be written raises a RuntimeError.

write_blif(network: technology_network, filename: str) → None

write_blif(network: aig_network, filename: str) → None

write_blif(network: xag_network, filename: str) → None

write_blif(network: mig_network, filename: str) → None

Writes the network as a BLIF file. A file that cannot be written raises a RuntimeError.

write_aiger(network: aig_network, filename: str) → None

Writes the AIG as a binary AIGER file, including its input, output, and network names. A file that cannot be written raises a RuntimeError.