Mapping Cartesian to Hexagonal Layouts

This algorithm maps Cartesian 2DDWave-clocked layouts used for Quantum-dot Cellular Automata (QCA) to hexagonal row-clocked layouts, which are suitable for Silicon Dangling Bonds (SiDBs).

The respective coordinates on the hexagonal grid are calculated as follows:

\[ y_{\mathit{hex}} = x_{\mathit{Cart}} + y_{\mathit{Cart}} \]
\[ x_{\mathit{hex}} = x_{\mathit{Cart}} + \left \lceil{\left \lfloor{\frac{h}{2}} \right \rfloor} - \frac{y_{\mathit{hex}}}{2}\right \rceil \]
Mapping a Cartesian 2DDWave-clocked layout onto a hexagonal row-clocked layout

Header: fiction/physical_design/hexagonalization.hpp

struct hexagonalization_params

This structure encapsulates settings that determine how primary inputs (PIs) and primary outputs (POs) are handled during the conversion from a Cartesian to a hexagonal layout.

Public Types

enum class io_pin_extension_mode : std::uint8_t

Specifies how primary inputs/outputs should be handled in the hexagonalization process.

Values:

enumerator NONE

Do not extend primary inputs/outputs to the top/bottom row (default).

enumerator EXTEND

Extend primary inputs/outputs to the top/bottom row.

enumerator EXTEND_PLANAR

Extend primary inputs/outputs to the top/bottom row with planar rerouting (i.e., without crossings).

Public Members

io_pin_extension_mode input_pin_extension = io_pin_extension_mode::NONE

Input extension mode. Defaults to none

io_pin_extension_mode output_pin_extension = io_pin_extension_mode::NONE

Output extension mode. Defaults to none

utils::progress_callback on_progress = {}

Callback that receives the progress of the gate mapping and the pin extension.

struct hexagonalization_stats

This struct stores statistics about the hexagonalization process.

Public Functions

inline void report(std::ostream &out = std::cout) const

Reports the statistics to the given output stream.

Parameters:

out – Output stream.

Public Members

mockturtle::stopwatch::duration time_total = {0}

Runtime of the hexagonalization process.

uint64_t x_size = {0ull}

Layout width.

uint64_t y_size = {0ull}

Layout height.

uint64_t num_gates = {0ull}

Number of gates.

uint64_t num_wires = {0ull}

Number of physical wires, excluding primary inputs and outputs.

uint64_t num_crossings = {0ull}

Number of crossings.

template<typename HexLyt, typename CartLyt>
HexLyt fiction::physical_design::hexagonalization(const CartLyt &lyt, const hexagonalization_params &params = {}, hexagonalization_stats *stats = nullptr)

Transforms a 2DDWave-clocked Cartesian layout into a hexagonal even row clocked layout suitable for SiDBs by remapping all gates and wires as originally proposed in “Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel” by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2023 (https://ieeexplore.ieee.org/document/10231278).

Template Parameters:

  • HexLyt – Even-row hexagonal gate-level layout return type.

  • CartLyt – Input Cartesian gate-level layout type.

Parameters:

  • lyt – 2DDWave-clocked Cartesian gate-level layout to hexagonalize.

  • params – Parameters.

  • stats – Statistics.

Throws:

  • std::invalid_argument – If clocking or placed geometry does not satisfy the input contract.

  • std::overflow_error – If the transformed coordinates exceed the signed coordinate range.

Returns:

Hexagonal representation of the Cartesian layout.

class hexagonalization_params

This structure encapsulates settings that determine how primary inputs (PIs) and primary outputs (POs) are handled during the conversion from a Cartesian to a hexagonal layout.

property input_pin_extension

Input extension mode. Defaults to none

property on_progress

Callback that receives the progress of the gate mapping and the pin extension.

property output_pin_extension

Output extension mode. Defaults to none

class hexagonalization_stats

This struct stores statistics about the hexagonalization process.

property num_crossings

Number of crossings.

property num_gates

Number of gates.

property num_wires

Number of physical wires, excluding primary inputs and outputs.

property time_total

Runtime of the hexagonalization process.

property x_size

Layout width.

property y_size

Layout height.

hexagonalization(layout: cartesian_gate_layout, parameters: hexagonalization_params = <mnt.pyfiction.physical_design.hexagonalization_params object at 0x579c36e20e50>, statistics: hexagonalization_stats | None = None) → hexagonal_gate_layout

Transforms a 2DDWave-clocked Cartesian layout into a hexagonal even row clocked layout suitable for SiDBs by remapping all gates and wires as originally proposed in "Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel" by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2023 (https://ieeexplore.ieee.org/document/10231278).

Parameters:

  • lyt – 2DDWave-clocked Cartesian gate-level layout to hexagonalize.

  • params – Parameters.

  • stats – Statistics.

Template Args:

  • HexLyt – Even-row hexagonal gate-level layout return type.

  • CartLyt – Input Cartesian gate-level layout type.

Returns:

Hexagonal representation of the Cartesian layout.

Raises:

  • std::invalid_argument – If clocking or placed geometry does not satisfy the input contract.

  • std::overflow_error – If the transformed coordinates exceed the signed coordinate range.