Determine Clocking

Header: fiction/physical_design/determine_clocking.hpp

Determines a new clock number assignment for the given gate-level layout. Whether the layout has useful/valid clocking information or not, this function will override each gate and wire segment with new clocking information if a valid clock number assignment exists.

struct determine_clocking_params

Parameters for the determine_clocking algorithm.

Public Members

bill::solvers sat_engine = bill::solvers::bsat2

The SAT solver to use.

struct determine_clocking_stats

Statistics for the determine_clocking algorithm.

Public Functions

inline void report(std::ostream &out = std::cout) const

Reports the statistics to the given output stream.

Parameters:

out – The output stream to report to.

Public Members

mockturtle::stopwatch::duration time_total = {0}

Total runtime.

template<typename Lyt>
bool fiction::physical_design::determine_clocking(Lyt &lyt, const determine_clocking_params &params = {}, determine_clocking_stats *stats = nullptr)

Determines clock numbers for the given (unclocked) gate-level layout. This algorithm parses the layout’s gate and wire connections, disregarding any existing clocking information, and constructs a SAT instance to find a valid clock number assignment under which the information flow is respected. On success, occupied clock zones use the solved phases. The stored clocking scheme retains its name and phase count.

All objects must lie inside the frame, every input must be connected to an adjacent source, and connections must be acyclic. Existing clock assignments need not respect those connections. Clock zones span all layers.

If no valid clock number assignment exists for lyt, this function returns false. Failure preserves the layout and its clocking scheme. A successful assignment preserves synchronization delays and unoccupied clock overrides.

This algorithm was proposed in “Ending the Tyranny of the Clock: SAT-based Clock Number Assignment for Field-coupled Nanotechnologies” by M. Walter, J. Drewniok, and R. Wille in IEEE NANO 2024 (https://ieeexplore.ieee.org/abstract/document/10628908).

Template Parameters:

Lyt – Gate-level layout type.

Parameters:

  • lyt – The gate-level layout to assign clock numbers to.

  • params – Parameters.

  • stats – Statistics.

Throws:

  • std::invalid_argument – If placement or declared connections violate the required topology.

  • std::bad_alloc – If allocation fails.

Returns:

true iff lyt could be successfully clocked via a valid clock number assignment.