On-the-fly SiDB Circuit Design

Placed and routed layouts

The circuit designer implements each tile of a hexagonal gate-level layout with SiDBs. The input must be placed and routed with port orientations supported by the Bestagon skeletons. Convert Cartesian layouts with Mapping Cartesian to Hexagonal Layouts before designing the SiDB circuit.

The default search uses exhaustive gate design with one canvas SiDB and stops at the first solution. Crossings and double wires use predefined implementations when possible. The required number of canvas SiDBs depends on the gates; the example uses three with QuickCell. The returned layout can be exported as SVG or SiQAD SQD.

The circuit’s timeout covers all gate designs; design_gate_params.operational_params.timeout can impose a shorter per-gate limit. Both use milliseconds; see Timeouts for defaults and limits.

Header: fiction/technology/sidb/generators/on_the_fly_circuit_design.hpp

struct on_the_fly_circuit_design_params

This struct stores the parameters to design an SiDB circuit.

Public Members

sidb::on_the_fly_gate_library_params sidb_on_the_fly_gate_library_parameters = {}

Parameters for the SiDB on-the-fly gate library.

uint64_t timeout = std::numeric_limits<uint64_t>::max()

Total timeout in milliseconds for all gates and layout conversion. The maximum value means unlimited; zero expires immediately. Every gate shares the same deadline, including crossings and double wires. Timeout checks are cooperative; allocation and non-interruptible setup can exceed the budget.

template<typename GateLyt>
layout fiction::sidb::generators::on_the_fly_circuit_design(const GateLyt &gate_lyt, const on_the_fly_circuit_design_params &params = {})

Designs a lattice-based SiDB circuit for a placed and routed pointy-top hexagonal gate-level layout.

The function validates every gate type before designing the SiDB implementations.

Template Parameters:

GateLyt – Pointy-top hexagonal gate-level layout type.

Parameters:

  • gate_lyt – Pointy-top hexagonal gate-level layout.

  • params – The parameters used for designing the circuit, encapsulated in an on_the_fly_circuit_design_params object.

Throws:

  • std::invalid_argument – if gate mapping uses a column arrangement instead of a row arrangement.

  • fcn::unsupported_gate_type_exception – if any object has an unsupported function.

  • unsuccessful_gate_design_error – if a gate cannot be designed.

  • utils::timeout_error – if the shared circuit budget or an individual gate budget expires. No partial circuit is returned. Deadline checks are cooperative and do not interrupt allocation or cell placement.

Returns:

Layout representing the designed SiDB circuit.

The Python call accepts hexagonal_gate_layout and returns sidb_layout. The call leaves its input unchanged and releases the GIL during circuit design. An unsupported gate type or orientation raises ValueError; an unsuccessful gate search raises RuntimeError. This interface does not accept defective surfaces or logic networks.

Choose the gate-search algorithm through design_gate_params.design_mode, as shown below. The PRUNING_ONLY mode skips operational simulation, so it does not verify the designed gates’ functionality.

from mnt.pyfiction.layouts import hexagonal_gate_layout
from mnt.pyfiction.sidb.generators import (
    design_sidb_gates_mode,
    on_the_fly_sidb_circuit_design,
    on_the_fly_sidb_circuit_design_params,
)
from mnt.pyfiction.sidb.io import write_sqd_layout

layout = hexagonal_gate_layout((2, 2, 0), "ROW", "AND")
a = layout.create_pi("a", (0, 0, 0))
b = layout.create_pi("b", (1, 0, 0))
gate = layout.create_and(a, b, (1, 1, 0))
layout.create_po(gate, "f", (0, 2, 0))

params = on_the_fly_sidb_circuit_design_params()
params.timeout = 60_000  # one minute for the whole circuit
gates = params.sidb_on_the_fly_gate_library_parameters.design_gate_params
gates.design_mode = design_sidb_gates_mode.QUICKCELL
gates.number_of_canvas_sidbs = 3
circuit = on_the_fly_sidb_circuit_design(layout, params)
write_sqd_layout(circuit, "and.sqd")
class sidb_complex_gate_design_policy(*values)

This struct represents the policy for complex (i.e., crossing, double wire, half-adder) gate design.

USING_PREDEFINED = 0
DESIGN_ON_THE_FLY = 1
class sidb_on_the_fly_gate_library_params

This struct encapsulates parameters for the parameterized SiDB gate library.

property canvas_sidb_complex_gates

This variable defines the number of canvas SiDBs dedicated to complex gates, such as crossing, double wire, and half-adder.

property design_gate_params

This struct holds parameters to design SiDB gates.

property influence_radius_charged_defects

This variable specifies the radius in nanometers around the center of the hexagon where atomic defects are incorporated into the gate design.

property using_predefined_crossing_and_double_wire_if_possible

This variable specifies the policy for complex gate design.

class on_the_fly_sidb_circuit_design_params

This struct stores the parameters to design an SiDB circuit.

property sidb_on_the_fly_gate_library_parameters

Parameters for the SiDB on-the-fly gate library.

property timeout

Total timeout in milliseconds for all gates and layout conversion. The maximum value means unlimited; zero expires immediately. Every gate shares the same deadline, including crossings and double wires. Timeout checks are cooperative; allocation and non-interruptible setup can exceed the budget.

on_the_fly_sidb_circuit_design(layout: hexagonal_gate_layout, params: on_the_fly_sidb_circuit_design_params = <mnt.pyfiction.sidb.generators.on_the_fly_sidb_circuit_design_params object at 0x579c36dfa8e0>) → sidb_layout

Design an SiDB circuit from a placed and routed pointy-top hexagonal gate-level layout.

The layout and parameters are copied before releasing the GIL. The input layout is not modified. This function does not perform placement and routing or accept a defective surface. The optional timeout bounds the whole circuit search in milliseconds. Deadline checks are cooperative; use a separate process when an exact cutoff is required. A timeout never returns a partial circuit.

Parameters:

  • layout – A pointy-top hexagonal gate-level layout with a row arrangement and supported Bestagon port orientations.

  • params – Circuit and individual-gate design parameters.

Returns:

An SiDB layout that can be exported with write_sqd_layout or write_sidb_layout_svg.

Raises:

  • TimeoutError – The circuit or an individual gate exceeds its timeout.

  • RuntimeError – A gate cannot be designed with the supplied parameters.

  • ValueError – Gate mapping uses a column arrangement, a gate type or orientation is unsupported, or gate parameters are invalid.

Defective surfaces

The C++ interface for defective surfaces requires Z3. It excludes gate-tile combinations whose skeletons overlap neutral defects, then uses exact for placement and routing. The gate designer implements the placed tiles while accounting for the surface’s defects.

If gate design fails, the algorithm blacklists the failing gate-tile-port combination and retries placement and routing. It raises unsuccessful_pr_error when no placement is possible.

Header: fiction/technology/sidb/generators/on_the_fly_circuit_design.hpp

struct on_the_fly_circuit_design_on_defective_surface_params

This struct stores the parameters to design an SiDB circuit on a defective surface.

Public Members

sidb::on_the_fly_gate_library_params sidb_on_the_fly_gate_library_parameters = {}

Parameters for the SiDB on-the-fly gate library.

physical_design::exact_physical_design_params exact_design_parameters = {}

Parameters for the exact placement and routing algorithm. The arrangement of the lattice tiling replaces layout_arrangement.

uint64_t timeout = std::numeric_limits<uint64_t>::max()

Total millisecond budget across surface analysis, placement-and-routing retries, and gate design. The maximum value means unlimited; zero expires immediately. Cancellation is cooperative.

template<typename GateLyt>
struct on_the_fly_circuit_design_on_defective_surface_stats

Statistics for the on-the-fly defect-aware circuit design.

Template Parameters:

GateLyt – Gate-level layout type.

Public Members

mockturtle::stopwatch::duration time_total = {0}

The total runtime of the on-the-fly circuit design.

physical_design::exact_physical_design_stats exact_stats = {}

The stats of the exact algorithm.

std::optional<GateLyt> gate_layout = {}

The gate-level layout after P&R.

template<typename Ntk, typename GateLyt>
layout fiction::sidb::generators::on_the_fly_circuit_design_on_defective_surface(const Ntk &ntk, const GateLyt &lattice_tiling, const layout &defective_surface, const on_the_fly_circuit_design_on_defective_surface_params &params = {}, on_the_fly_circuit_design_on_defective_surface_stats<GateLyt> *stats = nullptr)

Implements an on-the-fly circuit design algorithm for a defective SiDB surface.

The process begins with placement and routing using a blacklist and the exact method. The blacklist includes skeleton-tile pairs that are excluded due to collisions between skeleton and neutral defects on specific tiles. After identifying a valid placement and routing, a defect-aware SiDB gate design algorithm is applied. This algorithm designs gates for each tile while accounting for atomic defects. If the gate design is unsuccessful, the blacklist is updated with the problematic skeleton-gate pair, and the placement and routing process is restarted. If the gate design succeeds, the algorithm finalizes the design and returns the SiDB circuit. This approach ensures that the circuit remains functional even in the presence of defects.

This methodology is detailed in the paper “On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond

Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024 (

https://ieeexplore.ieee.org/abstract/document/10628962).

Note

A circuit or gate timeout aborts the operation. Only a completed, unsuccessful gate search blacklists a tile.

Template Parameters:

  • Ntk – The type of the input network.

  • GateLyt – Gate-level layout type.

Parameters:

  • ntk – The input network to be mapped onto the defective surface.

  • lattice_tiling – The lattice tiling used for the circuit design.

  • defective_surface – The defective surface on which the SiDB circuit is designed.

  • params – The parameters used for designing the circuit, encapsulated in an on_the_fly_circuit_design_on_defective_surface_params object.

  • stats – Pointer to a structure for collecting statistics. If nullptr, statistics are discarded.

Throws:

  • utils::timeout_error – If a circuit or gate-design timeout expires.

  • std::invalid_argument – If the simulation engine does not support the requested gate-design timeout.

Returns:

Layout representing the designed circuit on the defective surface.