SiDB Gate Designer

Set operational_params.timeout in milliseconds to limit a gate search. See Timeouts for defaults, exceptions, and cancellation limits.

Header: fiction/technology/sidb/generators/design_gates.hpp

struct design_gates_stats

Statistics of the gate designers.

Public Functions

inline void report(std::ostream &out = std::cout) const

Prints the statistics.

Parameters:

out – The stream to print to.

Public Members

mockturtle::stopwatch::duration time_total = {0}

Total runtime.

mockturtle::stopwatch::duration pruning_total = {0}

Runtime of the pruning.

simulation::engine sim_engine = {simulation::engine::QUICKEXACT}

The simulation engine used.

std::size_t number_of_layouts = {0}

Number of canvas layouts, saturated at std::size_t’s maximum.

std::size_t number_of_layouts_after_first_pruning = {0}

Number of canvas layouts that survived the first pruning filter.

std::size_t number_of_layouts_after_second_pruning = {0}

Number of canvas layouts that survived the second pruning filter.

std::size_t number_of_layouts_after_third_pruning = {0}

Number of canvas layouts that survived the third pruning filter.

struct design_gates_params

Parameters of the gate designers.

Public Types

enum class termination_condition : uint8_t

When to stop.

Values:

enumerator AFTER_FIRST_SOLUTION

Stop after the first operational gate.

enumerator ALL_COMBINATIONS_ENUMERATED

Enumerate every combination of canvas SiDBs.

enum class design_gates_mode : uint8_t

The design mode.

Values:

enumerator QUICKCELL

QuickCell: prune the canvas layouts with the filters of the operational check, then simulate the rest.

enumerator AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER

Simulate every canvas layout.

enumerator RANDOM

Place canvas SiDBs at random until an operational gate is found or the attempt limit is reached.

enumerator PRUNING_ONLY

Only run the pruning filters of QuickCell and return the surviving candidates.

Public Members

simulation::logic::is_operational_params operational_params = {}

Parameters of the operational check.

design_gates_mode design_mode = design_gates_mode::AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER

The design mode.

std::pair<lattice_site, lattice_site> canvas = {site_at_row(24, 17), site_at_row(34, 28)}

The canvas: the area canvas SiDBs are placed in, as two opposite corners.

std::size_t number_of_canvas_sidbs = 1

Number of canvas SiDBs.

std::size_t maximal_random_design_attempts = 1'000'000

Maximum number of layouts evaluated by random gate design across all threads.

termination_condition termination_cond = termination_condition::AFTER_FIRST_SOLUTION

When to stop.

utils::progress_callback on_progress = {}

Callback that receives the progress of the design mode’s main loop.

inline std::vector<layout> fiction::sidb::generators::design_gates(const layout &skeleton, const std::vector<kitty::dynamic_truth_table> &spec, const design_gates_params &params = {}, design_gates_stats *stats = nullptr)

Designs SiDB gates on a skeleton: canvas SiDBs are placed in the canvas area so that the skeleton’s input and output wires implement the given Boolean function(s). The design mode chooses between simulating every combination of canvas SiDBs, QuickCell’s pruning followed by simulation, random placement, and pruning only. Worker exceptions propagate to the caller after all started workers finish. Random placement samples at most maximal_random_design_attempts candidates without enumerating canvas layouts. The timeout covers setup and all search phases. Expiration discards partial results and stops all workers before throwing. Allocation and non-interruptible setup may exceed the cooperative deadline.

QuickCell is described in “Towards Fast Automatic Design of Silicon Dangling Bond Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in DATE 2025 (https://ieeexplore.ieee.org/abstract/document/10992885

) and “QuickCell: Fast Automatic Design of Standard Cells

for Silicon Dangling Bond Logic” by the same authors in TCAD 2025 (

https://ieeexplore.ieee.org/document/11146893

). The exhaustive designer is described in “Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on

Silicon Dangling Bonds” by J. Drewniok, M. Walter, and R. Wille in NANOARCH 2023 (

https://dl.acm.org/doi/10.1145/3611315.3633241).

Parameters:

  • skeleton – The skeleton with its input and output wires.

  • spec – The Boolean function(s) to implement; must not be empty.

  • params – Parameters.

  • stats – Statistics.

Throws:

  • std::invalid_argument – if spec is empty or the input wire count differs from the specification.

  • utils::timeout_error – if the gate-design deadline is reached.

Returns:

The designed gates.

The Python call releases the GIL and leaves the input skeleton unchanged.

params = design_sidb_gates_params()
params.operational_params.timeout = 5_000  # milliseconds
gates = design_sidb_gates(skeleton, specification, params)
class design_sidb_gates_stats

Statistics of the gate designers.

class design_sidb_gates_params

Parameters of the gate designers.

property canvas

the area canvas SiDBs are placed in, as two opposite corners.

Type:

The canvas

property design_mode

The design mode.

property maximal_random_design_attempts

Maximum number of layouts evaluated by random gate design across all threads.

property number_of_canvas_sidbs

Number of canvas SiDBs.

property on_progress

Callback that receives the progress of the design mode’s main loop.

property operational_params

Parameters of the operational check.

property termination_cond

When to stop.

class design_sidb_gates_mode(*values)

The design mode.

QUICKCELL = 0
AUTOMATIC_EXHAUSTIVE_GATE_DESIGNER = 1
RANDOM = 2
PRUNING_ONLY = 3
class termination_condition(*values)
design_sidb_gates(skeleton: mnt.pyfiction.sidb.sidb_layout, spec: collections.abc.Sequence[mnt.pyfiction.synthesis.dynamic_truth_table], params: mnt.pyfiction.sidb.generators.design_sidb_gates_params = <mnt.pyfiction.sidb.generators.design_sidb_gates_params object at 0x579c36df5c90>, stats: mnt.pyfiction.sidb.generators.design_sidb_gates_stats | None = None) → list[sidb_layout]

Designs SiDB gates on a skeleton: canvas SiDBs are placed in the canvas area so that the skeleton’s input and output wires implement the given Boolean function(s). The design mode chooses between simulating every combination of canvas SiDBs, QuickCell’s pruning followed by simulation, random placement, and pruning only.

Worker exceptions propagate to the caller after all started workers finish.

Random placement samples at most maximal_random_design_attempts candidates without enumerating canvas layouts.

The timeout covers setup and all search phases. Expiration discards partial results and stops all workers before throwing. Allocation and non-interruptible setup may exceed the cooperative deadline.

QuickCell is described in “Towards Fast Automatic Design of Silicon Dangling Bond Logic” by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in DATE 2025 (https://ieeexplore.ieee.org/abstract/document/10992885) and “QuickCell: Fast Automatic Design of Standard Cells for Silicon Dangling Bond Logic” by the same authors in TCAD 2025 (https://ieeexplore.ieee.org/document/11146893). The exhaustive designer is described in “Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds” by J. Drewniok, M. Walter, and R. Wille in NANOARCH 2023 (https://dl.acm.org/doi/10.1145/3611315.3633241).

Parameters:

  • skeleton – The skeleton with its input and output wires.

  • spec – The Boolean function(s) to implement; must not be empty.

  • params – Parameters.

  • stats – Statistics.

Returns:

The designed gates.

Raises:

  • std::invalid_argument – if spec is empty or the input wire count differs from the specification.

  • utils::timeout_error – if the gate-design deadline is reached.